Various devices require operation with low power consumption. For example, hand-held communication devices require such low power consumption and, in particular, implantable medical devices require low power capabilities. With respect to implantable medical devices, for example, microprocessor-based implantable cardiac devices, such as implantable pacemakers and defibrillators, are required to operate with a lower power consumption to increase battery life and device longevity.
Generally, such low power devices are designed using complementary metal oxide semiconductor (CMOS) technology. CMOS technology is generally used because such technology has the characteristic of substantially zero "static" power consumption.
Power consumption of CMOS circuits consists generally of two power consumption factors, namely "dynamic" power consumption and static power consumption. Static power consumption is only due to current leakage as the quiescent current of such circuits is zero. Dynamic power consumption is the dominant factor of power consumption for CMOS technology. Dynamic power consumption is basically due to the current required to charge internal and load capacitances during switching, i.e., the charging and discharging of such capacitances. Dynamic power (P) equals: 1/2CV.sub.DD.sup.2 F, where C is nodal capacitance, F is the clock or switching frequency, and V.sub.DD is the supply voltage for the CMOS circuit. As can be seen from the formula for calculating dynamic power (P), such dynamic power consumption of CMOS circuits is proportional to the square of the supply voltage (V.sub.DD). In addition, dynamic power (P) is proportional to switching or clock frequency (F).
In accordance with the formula for dynamic power consumption, it has been effective in conventional CMOS integrated circuit designs to scale down the supply voltage for an entire device (e.g., hybrid) or integrated circuit (IC), i.e., operate the circuit at low supply voltages, to reduce power consumption for such designs. For example, in the MEDTRONIC SPECTRAX.RTM. device of circa 1979, IC circuitry was powered by one lithium iodine cell (as opposed to the two cells of the prior art). This reduced the supply voltage to 2.8 volts from 5.6 volts, thus reducing overhead current. Voltages required to be greater than 2.8 volts were generated by a voltage doubler, or alternatively by a charge pump (e.g., output pacing pulses). Further, for example, in the MEDTRONIC SYMBIOS.RTM. device of circa 1983, logic circuitry was powered by a voltage regulator controlling the IC supply voltage to a "sum of thresholds" supply. This regulator provided a supply to the IC (i.e., V.sub.DD) of several hundred millivolts above the sum of the n-channel and p-channel thresholds of the CMOS transistors making up the IC. This regulator was self calibrating regarding manufacturing variations of the transistor thresholds.
Other devices have reduced power consumption in other manners. For example, various device designs have shut-down analog blocks and/or shut-off clocks to logic blocks not being used at particular times, thereby reducing power. Further, for example, microprocessor based devices have historically used a "burst clock" design to operate a microprocessor at a very high clock rate (e.g., generally 500-1000 Kilohertz (KHz)), for relatively short periods of time to gain the benefit of a "duty cycle" to reduce average current drain. A much lower frequency clock (e.g., generally 32 KHz) is used for other circuitry and/or the processor when not in the high clock rate mode, i.e., burst clock mode. Many known processor based implanted devices utilize the burst clock technique. For example, implanted devices available from Medtronic, Vitatron, Biotronic, ELA, Intermedics, Pacesetters, InControl, Cordis, CPI, etc., utilize burst clock techniques. A few illustrative examples which describe the use of a burst clock are provided in U.S. Pat. No. 4,561,442 to Vollmann et al., entitled "Implantable Cardiac Pacer With Discontinuous Microprocessor Programmable Anti Tachycardia Mechanisms and Patient Data Telemetry," issued Dec. 31, 1985; U.S. Pat. No. 5,022,395 to Russie, entitled "Implantable Cardiac Device With Dual Clock Control of Microprocessor," issued Jun. 11, 1991; U.S. Pat. No. 5,388,578 to Yomtov et al., entitled "Improved Electrode System For Use With An Implantable Cardiac Patient Monitor," issued Feb. 14, 1995; and U.S. Pat. No. 5,154,170 to Bennett et al., entitled "Optimization for Rate Responsive Cardiac Pacemaker," issued Oct. 13, 1992.
FIG. 1 represents a graphical illustration of energy/delay versus supply voltage for CMOS circuits such as a CMOS inverter 10 shown in FIG. 2 for illustrative purposes. The inverter 10 is provided with a supply voltage, V.sub.DD, which is connected to the source of a PMOS field effect transistor (FET) 12. PMOS FET 12 has its drain connected to the drain of an NMOS FET 14 whose source is connected to ground. In this configuration, an input V.sub.i applied to both the gates of FETs 12, 14 is inverted to provide output V.sub.o. Simply stated, one clock cycle, or logic level change, is used to invert the input V.sub.i to V.sub.o.
As shown in FIG. 1, the circuit logic delay increases drastically as the supply voltage is reduced to near one volt, as represented by delay line 16 and energy/delay line 18. As such, reducing of the supply voltage (V.sub.DD) continuously to lower levels is impractical because of the need for higher supply voltages when higher frequency operation is required. For example, generally CMOS logic circuits must periodically provide functionality at a higher frequency, e.g., burst clock frequency. However, as the supply voltage (V.sub.DD) is decreased, such energy consumption is reduced by the square of the supply voltage (V.sub.DD) as is shown by energy consumption line 20. Therefore, speed requires a higher supply voltage (V.sub.DD) which is in direct conflict with low power consumption.
Other problems are also evident when lower supply voltages (V.sub.DD) are used for CMOS circuit designs. When a lower supply voltage is selected, static leakage current losses may arise, particularly at lower frequencies, due to increased static leakage current losses.
Various techniques for reducing power consumption in devices are known in the art, some examples of which may be found in at least some of the references listed in Table 1 below.
TABLE 1 ______________________________________ Patent No. Inventor Issue Date ______________________________________ 4,031,899 Renirie June 28, 1977 4,460,835 Masuoka July 17, 1984 4,561,442 Vollmann et al. Dec. 31, 1985 4,791,318 Lewis et al. Dec. 13, 1988 5,022,395 Russie June 11, 1991 5,154,170 Bennett et al. Oct. 13, 1992 5,185,535 Farb et al. Feb. 9, 1993 5,187,796 Wang et al. Feb. 16, 1993 5,388,578 Yomtov et al. Feb. 14, 1995 5,610,083 Chan et al. Mar. 11, 1997 ______________________________________
All references listed in Table 1 above are hereby incorporated by reference herein, each in its respective entirety. As those of ordinary skill in the art will appreciate readily upon reading the Summary of the Invention, Detailed Description of the Embodiments, and Claims set forth below, at least some of the devices and methods disclosed in the publications, patents or patent applications referenced in the present application, including those disclosed in the references listed in Table 1 above, may be modified advantageously in accordance with the teachings of the present invention.